Output bit selection methodology for test response compaction

Wei Cheng Lien, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution


In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Test Conference, ITC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467387736
Publication statusPublished - 2016 Jul 2
Event47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
Duration: 2016 Nov 152016 Nov 17

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Other47th IEEE International Test Conference, ITC 2016
Country/TerritoryUnited States
CityFort Worth

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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