Output bit selection methodology for test response compaction

Wei Cheng Lien, Kuen Jong Lee

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE International Test Conference, ITC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467387736
DOIs
Publication statusPublished - 2016 Jul 2
Event47th IEEE International Test Conference, ITC 2016 - Fort Worth, United States
Duration: 2016 Nov 152016 Nov 17

Publication series

NameProceedings - International Test Conference
Volume0
ISSN (Print)1089-3539

Other

Other47th IEEE International Test Conference, ITC 2016
CountryUnited States
CityFort Worth
Period16-11-1516-11-17

Fingerprint

Compaction
Methodology
Output
Networks (circuits)
Product design
Fault
Diagnosability
Industrial Design
Testing
Aliasing
Test Set
Costs
Compact Set
Tolerance
Percentage
Unknown
Subset
Zero
Experimental Results

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Lien, W. C., & Lee, K. J. (2016). Output bit selection methodology for test response compaction. In Proceedings - 2016 IEEE International Test Conference, ITC 2016 [7805873] (Proceedings - International Test Conference; Vol. 0). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/TEST.2016.7805873
Lien, Wei Cheng ; Lee, Kuen Jong. / Output bit selection methodology for test response compaction. Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (Proceedings - International Test Conference).
@inproceedings{4f539a7c8de144b2a0bcbf7a6ebba329,
title = "Output bit selection methodology for test response compaction",
abstract = "In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10{\%} of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27{\%} of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.",
author = "Lien, {Wei Cheng} and Lee, {Kuen Jong}",
year = "2016",
month = "7",
day = "2",
doi = "10.1109/TEST.2016.7805873",
language = "English",
series = "Proceedings - International Test Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "Proceedings - 2016 IEEE International Test Conference, ITC 2016",
address = "United States",

}

Lien, WC & Lee, KJ 2016, Output bit selection methodology for test response compaction. in Proceedings - 2016 IEEE International Test Conference, ITC 2016., 7805873, Proceedings - International Test Conference, vol. 0, Institute of Electrical and Electronics Engineers Inc., 47th IEEE International Test Conference, ITC 2016, Fort Worth, United States, 16-11-15. https://doi.org/10.1109/TEST.2016.7805873

Output bit selection methodology for test response compaction. / Lien, Wei Cheng; Lee, Kuen Jong.

Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7805873 (Proceedings - International Test Conference; Vol. 0).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

TY - GEN

T1 - Output bit selection methodology for test response compaction

AU - Lien, Wei Cheng

AU - Lee, Kuen Jong

PY - 2016/7/2

Y1 - 2016/7/2

N2 - In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

AB - In this paper we propose an output-bit selection technique for test response compaction, with which only a subset of output response bits is selected for observation during testing. Advantages of this technique include zero aliasing, high compaction ratio, full X-Tolerance, low area overhead, simple test control and high diagnosability. Also no circuit/ ATPG modification is needed, hence this work can be easily integrated into any typical industrial design/test flow to significantly reduce test cost. Experimental results show that in general less than 10% of test response data of already very compact test sets are needed to detect all testable stuck-At or transition faults, with the reduction ratio increasing with the size of circuits, e.g., only 1.27% of output bits need be observed for b19 that contains more than 1M faults. Efficient test architectures to implement this technique are also presented, which include one that can deal with test responses containing high percentage of unknown values.

UR - http://www.scopus.com/inward/record.url?scp=85013980864&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85013980864&partnerID=8YFLogxK

U2 - 10.1109/TEST.2016.7805873

DO - 10.1109/TEST.2016.7805873

M3 - Conference contribution

AN - SCOPUS:85013980864

T3 - Proceedings - International Test Conference

BT - Proceedings - 2016 IEEE International Test Conference, ITC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Lien WC, Lee KJ. Output bit selection methodology for test response compaction. In Proceedings - 2016 IEEE International Test Conference, ITC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7805873. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2016.7805873