Output-bit selection with X-avoidance using multiple counters for test-response compaction

Wei Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong Yu Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Output-bit selection is a recently proposed test-response compaction approach that can effectively deal with aliasing, unknown-value, and low-diagnosis problems. This approach has been implemented using a single counter and a multiplexer without considering unknown values. Also, such an implementation may require the application of a pattern multiple times in order to observe all selected responses. In this paper, we present a multiple-counter-based architecture with a new selection algorithm that can avoid most unknown-values yet achieve high compaction ratio. The remaining small number of unknowns can then be dealt with using some simple masking logic. Experiments on IWLS'05 circuits show that even with 16% unknown responses, all unknown values can be handled with 88.92%93.21% response-volume reduction still achieved and only a moderate increase in test-application time.

Original languageEnglish
Title of host publicationProceedings - 2014 19th IEEE European Test Symposium, ETS 2014
PublisherIEEE Computer Society
ISBN (Print)9781479934157
DOIs
Publication statusPublished - 2014 Jan 1
Event19th IEEE European Test Symposium, ETS 2014 - Paderborn, Germany
Duration: 2014 May 262014 May 30

Publication series

NameProceedings - 2014 19th IEEE European Test Symposium, ETS 2014

Other

Other19th IEEE European Test Symposium, ETS 2014
CountryGermany
CityPaderborn
Period14-05-2614-05-30

All Science Journal Classification (ASJC) codes

  • Safety, Risk, Reliability and Quality

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