Output selection for test response compaction based on multiple counters

Wei Cheng Lien; Kuen-Jong Lee; Krishnendu Chakrabarty; Tong Yu Hsieh

doi:10.1109/VLSI-DAT.2014.6834865

Output selection for test response compaction based on multiple counters

Wei Cheng Lien, Kuen-Jong Lee, Krishnendu Chakrabarty, Tong Yu Hsieh

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.¹

Original language	English
Title of host publication	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Publisher	IEEE Computer Society
ISBN (Print)	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834865
Publication status	Published - 2014 Jan 1
Event	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan Duration: 2014 Apr 28 → 2014 Apr 30

Publication series

Name	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Other

Other	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
Country	Taiwan
City	Hsinchu
Period	14-04-28 → 14-04-30

All Science Journal Classification (ASJC) codes

Control and Systems Engineering

Access to Document

10.1109/VLSI-DAT.2014.6834865

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Lien, W. C., Lee, K-J., Chakrabarty, K., & Hsieh, T. Y. (2014). Output selection for test response compaction based on multiple counters. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834865] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834865

Lien, Wei Cheng ; Lee, Kuen-Jong ; Chakrabarty, Krishnendu ; Hsieh, Tong Yu. / Output selection for test response compaction based on multiple counters. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

@inproceedings{c681b8c96e2e47bd86cf444bf5afc96c,

title = "Output selection for test response compaction based on multiple counters",

abstract = "Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.1",

author = "Lien, {Wei Cheng} and Kuen-Jong Lee and Krishnendu Chakrabarty and Hsieh, {Tong Yu}",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/VLSI-DAT.2014.6834865",

language = "English",

isbn = "9781479927760",

series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

publisher = "IEEE Computer Society",

booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

address = "United States",

note = "2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 ; Conference date: 28-04-2014 Through 30-04-2014",

}

Lien, WC, Lee, K-J, Chakrabarty, K & Hsieh, TY 2014, Output selection for test response compaction based on multiple counters. in Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834865, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 14-04-28. https://doi.org/10.1109/VLSI-DAT.2014.6834865

Output selection for test response compaction based on multiple counters. / Lien, Wei Cheng; Lee, Kuen-Jong; Chakrabarty, Krishnendu; Hsieh, Tong Yu.

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834865 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Output selection for test response compaction based on multiple counters

AU - Lien, Wei Cheng

AU - Lee, Kuen-Jong

AU - Chakrabarty, Krishnendu

AU - Hsieh, Tong Yu

PY - 2014/1/1

Y1 - 2014/1/1

N2 - Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.1

AB - Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. This single-counter-based approach may need to apply one pattern several times in order to observe all selection responses, hence may significantly increase the test application time. To address this weakness, this paper presents a multiple-counter-based output selection method to observe more than one output response bits at each scan-out cycle. A new response selection algorithm is developed to determine desired responses under a set of pre-defined counter operations. Results on IWLS'05 benchmarks show that compared with the single counter-based scheme, the proposed method can reduce 47.33%∼67.87% test application time with only slight increase on area overhead.1

UR - http://www.scopus.com/inward/record.url?scp=84903973981&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84903973981&partnerID=8YFLogxK

U2 - 10.1109/VLSI-DAT.2014.6834865

DO - 10.1109/VLSI-DAT.2014.6834865

M3 - Conference contribution

AN - SCOPUS:84903973981

SN - 9781479927760

T3 - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

BT - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

PB - IEEE Computer Society

T2 - 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Y2 - 28 April 2014 through 30 April 2014

ER -

Lien WC, Lee K-J, Chakrabarty K, Hsieh TY. Output selection for test response compaction based on multiple counters. In Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834865. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). https://doi.org/10.1109/VLSI-DAT.2014.6834865