Oxide degradation mechanism in stacked-gate flash memory using the cell array stress test

Shih Hung Tsai, Jui Sheng Hung, Na Fu Wang, Jui Hong Horng, Mau Phon Houng, Yeong Her Wang

Research output: Contribution to journalArticlepeer-review

Abstract

The generation of oxide charges and interface states during the program/erase operation in flash memory has been known to degrade the tunnel oxide quality. However, there is still no effective method to analyse the endurance and disturbed performance of the flash memory at the test level. So in this paper, a simple and fast method is applied to characterize the endurance and disturbed performance on a 98K bit flash cell array stress test structure. Based on this structure, the behaviour of the weakest part of the memory array after the program/erase operation can be easily observed. Moreover, the effects of the oxide charges and interface states generated are also discussed. Also, excess hole trapping in the oxide leads to fast charge loss during the disturbance test. The fast charge loss caused by holes is the more serious of these two failure mechanisms because the relatively low high-state VT can be corrected by circuit-level, program/erase-verified sequences. However, poor disturbance characteristics cause logical errors during the reading of an array.

Original languageEnglish
Pages (from-to)857-863
Number of pages7
JournalSemiconductor Science and Technology
Volume18
Issue number9
DOIs
Publication statusPublished - 2003 Sep 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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