Oxide degradation mechanism in stacked-gate flash memory using the cell array stress test

The generation of oxide charges and interface states during the program/erase operation in flash memory has been known to degrade the tunnel oxide quality. However, there is still no effective method to analyse the endurance and disturbed performance of the flash memory at the test level. So in this paper, a simple and fast method is applied to characterize the endurance and disturbed performance on a 98K bit flash cell array stress test structure. Based on this structure, the behaviour of the weakest part of the memory array after the program/erase operation can be easily observed. Moreover, the effects of the oxide charges and interface states generated are also discussed. Also, excess hole trapping in the oxide leads to fast charge loss during the disturbance test. The fast charge loss caused by holes is the more serious of these two failure mechanisms because the relatively low high-state V_T can be corrected by circuit-level, program/erase-verified sequences. However, poor disturbance characteristics cause logical errors during the reading of an array.