P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

Chih Lung Lin; Chun Da Tu; Min Chin Chuang; Kuan Wen Chou; Chia Che Hung; Chih Wei Wang; Min Feng Chiang; Yung Chih Chen

doi:10.1889/1.3499952

P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

Chih Lung Lin
, Chun Da Tu
, Min Chin Chuang
, Kuan Wen Chou
, Chia Che Hung
, Chih Wei Wang
, Min Feng Chiang
, Yung Chih Chen

Department of Electrical Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

Original language	English
Pages (from-to)	1360-1362
Number of pages	3
Journal	Digest of Technical Papers - SID International Symposium
Volume	41 1
DOIs	https://doi.org/10.1889/1.3499952
Publication status	Published - 2010 May

All Science Journal Classification (ASJC) codes

General Engineering

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10.1889/1.3499952

Cite this

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title = "P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio",

abstract = "This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.",

author = "Lin, \{Chih Lung\} and Tu, \{Chun Da\} and Chuang, \{Min Chin\} and Chou, \{Kuan Wen\} and Hung, \{Chia Che\} and Wang, \{Chih Wei\} and Chiang, \{Min Feng\} and Chen, \{Yung Chih\}",

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AU - Lin, Chih Lung

AU - Tu, Chun Da

AU - Chuang, Min Chin

AU - Chou, Kuan Wen

AU - Hung, Chia Che

AU - Wang, Chih Wei

AU - Chiang, Min Feng

AU - Chen, Yung Chih

PY - 2010/5

Y1 - 2010/5

N2 - This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

AB - This paper presents a new a-Si:H gate driver circuit for large panel applications. Consisting of 12 TFTs and three capacitors, the proposed circuit is fabricated for measurement. The threshold voltage shift of TFTs is significantly reduced by reducing clock duty ratio. Experimental results indicate that the gate driver circuit operates stably under long-term and high temperature testing.

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SN - 0097-966X

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JO - Digest of Technical Papers - SID International Symposium

JF - Digest of Technical Papers - SID International Symposium

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P-39: A highly stable a-Si:H TFT gate driver circuit with reducing clock duty ratio

Abstract

All Science Journal Classification (ASJC) codes

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