Packet processing with blocking for bursty traffic on multi-thread network processor

Yeim Kuan Chang, Fang Chen Kuo

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

It is well-known that there are bursty accesses in network traffic. It means a burst of packets with the same meaningful headers are usually received by routers at the same time. With such traffic, routers usually perform the same computations and access the same memory location repeatedly. To utilize this characteristic of network traffic, many cache schemes are proposed to deal with the bursty access patterns. However, in the multi-thread network processor based routers, the existing cache schemes will not suit to the bursty traffic. Since all threads may all deal with the packets with the same headers, if the former threads do not update the cache entries yet, the subsequent threads still have to repeat the computations due to the cache miss. In this paper, we propose a cache scheme called B-cache for the multi-thread network processors. B-cache blocks the subsequent threads from doing the same computations which are being processed by the former thread. By applying B-cache, any packet processing tasks with high locality characteristic, such as IP address lookup, packet classification, and intrusion detection, can avoid the duplicate computations and hence achieve a better packet processing rate. We implement the proposed B-cache scheme on Intel IXP2400 network processor, the experimental results shows that our B-cache scheme can achieves the line speed of Intel IXP2400.

Original languageEnglish
Title of host publication2009 International Conference on High Performance Switching and Routing, HPSR 2009
DOIs
Publication statusPublished - 2009 Dec 1
Event2009 International Conference on High Performance Switching and Routing, HPSR 2009 - Paris, France
Duration: 2009 Jun 222009 Jun 24

Publication series

Name2009 International Conference on High Performance Switching and Routing, HPSR 2009

Other

Other2009 International Conference on High Performance Switching and Routing, HPSR 2009
CountryFrance
CityParis
Period09-06-2209-06-24

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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