TY - GEN
T1 - Parallel Dynamic Voltage and Frequency Scaling for stream decoding using a multicore embedded system
AU - Lai, Ying Xun
AU - Huang, Yueh Min
AU - Lai, Chin Feng
AU - Trajkovic, Ljiljana
PY - 2011/8/2
Y1 - 2011/8/2
N2 - Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS) may be used for simpler calculations in order to decrease the system voltage or frequency and achieve lower power consumption. Combining these two mechanisms may lead to higher efficiency and lower power consumption. In this paper, we introduce a parallel decoding process with Digital Signal Processing (DSP) for power efficiency in a heterogeneous multi-core embedded system. We describe a parallel low-power design on the system level. Under the condition of preserving the original decoding process, we manage the size of the system's multimedia buffer by considering the spontaneous streaming transfer and tuning the decoding process scheduling time by using the DVFS system in order to decrease the multimedia data dependency and achieve a multi-core embedded system with accurate and low-power detection mechanism.
AB - Parallel structures may be used to increase a system processing speed in case of large amount of data or highly complex calculations. Dynamic Voltage and Frequency Scaling (DVFS) may be used for simpler calculations in order to decrease the system voltage or frequency and achieve lower power consumption. Combining these two mechanisms may lead to higher efficiency and lower power consumption. In this paper, we introduce a parallel decoding process with Digital Signal Processing (DSP) for power efficiency in a heterogeneous multi-core embedded system. We describe a parallel low-power design on the system level. Under the condition of preserving the original decoding process, we manage the size of the system's multimedia buffer by considering the spontaneous streaming transfer and tuning the decoding process scheduling time by using the DVFS system in order to decrease the multimedia data dependency and achieve a multi-core embedded system with accurate and low-power detection mechanism.
UR - http://www.scopus.com/inward/record.url?scp=79960849248&partnerID=8YFLogxK
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U2 - 10.1109/ISCAS.2011.5937973
DO - 10.1109/ISCAS.2011.5937973
M3 - Conference contribution
AN - SCOPUS:79960849248
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1956
EP - 1959
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -