Parallel processing for deblocking filter in H.264/AVC

Chung Ming Chen; Chung-Ho Chen

Parallel processing for deblocking filter in H.264/AVC

Chung Ming Chen, Chung-Ho Chen

Institute of Computer and Communication Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

8 Citations (Scopus)

Abstract

In this paper, we propose an efficient parallel architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use six forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two sets of filter operation (each set contains four edge filter operations) to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Parallel Filtering Architecture (PFA)." As a result, the performance of PFA is 390% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced by 63% and 25% respectively compared to the basic and advanced architectures of the previous proposal.

Original language	English
Title of host publication	Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005
Editors	M.H. Hamza
Pages	188-191
Number of pages	4
Publication status	Published - 2005 Dec 1
Event	Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005 - Cambridge, MA, United States Duration: 2005 Oct 31 → 2005 Nov 2

Publication series

Name	Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005

Other

Other	Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005
Country	United States
City	Cambridge, MA
Period	05-10-31 → 05-11-02

All Science Journal Classification (ASJC) codes

Engineering(all)

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Cite this

Chen, C. M., & Chen, C-H. (2005). Parallel processing for deblocking filter in H.264/AVC. In M. H. Hamza (Ed.), Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005 (pp. 188-191). (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).

Chen, Chung Ming ; Chen, Chung-Ho. / Parallel processing for deblocking filter in H.264/AVC. Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. editor / M.H. Hamza. 2005. pp. 188-191 (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).

@inproceedings{4fb9ab099549496688a2c4c6f5bf7610,

title = "Parallel processing for deblocking filter in H.264/AVC",

abstract = "In this paper, we propose an efficient parallel architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use six forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two sets of filter operation (each set contains four edge filter operations) to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called {"}Parallel Filtering Architecture (PFA).{"} As a result, the performance of PFA is 390% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced by 63% and 25% respectively compared to the basic and advanced architectures of the previous proposal.",

author = "Chen, {Chung Ming} and Chung-Ho Chen",

year = "2005",

month = dec,

day = "1",

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series = "Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005",

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booktitle = "Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005",

note = "Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005 ; Conference date: 31-10-2005 Through 02-11-2005",

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Chen, CM & Chen, C-H 2005, Parallel processing for deblocking filter in H.264/AVC. in MH Hamza (ed.), Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005, pp. 188-191, Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005, Cambridge, MA, United States, 05-10-31.

Parallel processing for deblocking filter in H.264/AVC. / Chen, Chung Ming; Chen, Chung-Ho.

Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005. ed. / M.H. Hamza. 2005. p. 188-191 (Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Parallel processing for deblocking filter in H.264/AVC

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N2 - In this paper, we propose an efficient parallel architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use six forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two sets of filter operation (each set contains four edge filter operations) to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Parallel Filtering Architecture (PFA)." As a result, the performance of PFA is 390% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced by 63% and 25% respectively compared to the basic and advanced architectures of the previous proposal.

AB - In this paper, we propose an efficient parallel architecture for the adaptive deblocking filter in H.264/AVC video coding standard. We use six forwarding shift register arrays (of which each contains 4×4 8-bit shift registers) with two transposing operations and two sets of filter operation (each set contains four edge filter operations) to support simultaneous processing of the horizontal and vertical filtering. The proposed architecture is called "Parallel Filtering Architecture (PFA)." As a result, the performance of PFA is 390% faster than the advanced architecture of the previous proposal. Moreover, the number of total memory references is reduced by 63% and 25% respectively compared to the basic and advanced architectures of the previous proposal.

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BT - Proceedings of the Fourth IASTED International Conference on Communications, Internet, and Information Technology, CIIT 2005

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