Parallel reconfigurable computing-based mapping algorithm for motion estimation in advanced video coding

Anand Paul; Yung Chuan Jiang; Jhing Fa Wang; Jar Ferr Yang

doi:10.1145/2331147.2331149

Parallel reconfigurable computing-based mapping algorithm for motion estimation in advanced video coding

Anand Paul, Yung Chuan Jiang, Jhing Fa Wang, Jar Ferr Yang

Institute of Computer and Communication Engineering

Research output: Contribution to journal › Article › peer-review

24 Citations (Scopus)

Abstract

Computational load of motion estimation in advanced video coding (AVC) standard is significantly high and even worse for HDTV and super-resolution sequences. In this article, a video processing algorithm is dynamically mapped onto a new parallel reconfigurable computing (PRC) architecture which consists of multiple dynamic reconfigurable computing (DRC) units. First, we construct a directed acyclic graph (DAG) to represent video coding algorithms in which motion estimation is the focus. A novel parallel partition approach is then proposed to map motion estimation DAG onto the multiple DRC units in a PRC system. This partitioning algorithm is capable of design optimization of parallel processing reconfigurable systems for a given number of processing elements in different search ranges. This speeds up the video processing with minimum sacrifice.

Original language	English
Article number	40
Journal	Transactions on Embedded Computing Systems
Volume	11
Issue number	SUPPL. 2
DOIs	https://doi.org/10.1145/2331147.2331149
Publication status	Published - 2012 Aug 1

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture

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