Parallelization of DVFS-enabled H.264/AVC decoder on heterogeneous multi-core platform

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Using a multi-core system to process real-time data of high computational complexity has become a popular solution for effectively enhancing system processing efficiency. However, the high-power consumption of a multi-core system remains a problem, particularly to handheld devices. Applying DVFS to properly decrease the system voltage and frequency can effectively save system power loss, nevertheless, the question of how to effectively and accurately configure a dynamic DVFS system to avoid missing a deadline or extra power loss remains to be widely discussed. This study examines many previous parallel processing architectures and DVFS mechanisms, and proposes two different orientations of parallel DVFS-enabled H.264/AVC decoders, and implements a multimedia heterogeneous multi-core platform. Based on experimental data, the impact of two parallel DVFS-able processing systems on H.264 decoding performance and power loss are studied.

Original languageEnglish
Title of host publicationProceedings - 2012 International Symposium on Computer, Consumer and Control, IS3C 2012
Pages157-160
Number of pages4
DOIs
Publication statusPublished - 2012 Jul 30
Event2012 International Symposium on Computer, Consumer and Control, IS3C 2012 - Taichung, Taiwan
Duration: 2012 Jun 42012 Jun 6

Publication series

NameProceedings - 2012 International Symposium on Computer, Consumer and Control, IS3C 2012

Other

Other2012 International Symposium on Computer, Consumer and Control, IS3C 2012
CountryTaiwan
CityTaichung
Period12-06-0412-06-06

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications

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