Peak-power reduction for multiple-scan circuits during test application

Kuen Jong Lee, Tsung Chu Huang, Jih Jeen Chen

Research output: Contribution to journalConference articlepeer-review

63 Citations (Scopus)


This paper proposes a novel method to reduce the peak power of multiple scan chain based circuits during testing. The peak periodicity and the peak width of the power waveforms for scan-based circuits are analyzed. An interleaving scan architecture based on adding delay buffers among the scan chains is proposed which can significantly reduce the peak power. This method can be efficiently employed in a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. The improvement percentage can be up to 50% when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, 76% of peak-power reduction can be achieved.

Original languageEnglish
Pages (from-to)453-458
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2000 Dec 1
Event9th Asian Test Symposium - Taipei, Taiwan
Duration: 2000 Dec 42000 Dec 6

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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