Performance-directed compaction for VLSI symbolic layouts

Lih Yang Wang, Yen Tai Lai, Bin-Da Liu, Tin Chung Chang

Research output: Contribution to journalArticlepeer-review


An effective approach for circuit performance improvement in VLSI symbolic layout compaction is presented. The approach is different from traditional approaches which aim at minimizing the total wire length; it directly optimizes the length of critical synchronous paths. Moreover, the critical synchronous paths are optimized before the layout size is minimized. The problem is so complicated that graph-theoretical algorithms for the general compaction problem cannot be used. Therefore, a new algorithm which consists of a graph-based technique and the simplex algorithm is proposed for the problem. Experimental results show that this algorithm is quite efficient.

Original languageEnglish
Pages (from-to)65-74
Number of pages10
JournalComputer-Aided Design
Issue number1
Publication statusPublished - 1995 Jan 1

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Industrial and Manufacturing Engineering

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