Performance-driven analog placement considering boundary constraint

Cheng Wu Lin, Jai Ming Lin, Chun Po Huang, Soon Jyh Chang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)


To reduce parasitic mismatches in analog design, we usually care about the property of symmetric placement for symmetry groups,which would form several symmetry islands in a chip. However, routing is greatly affected by placement results. If modules with nput or output ports are placed arbitrarily in a symmetry island, the routing wires, which connect these modules with other modules outside the island, may induce unwanted parasitics coupling to signals, and thus circuit performance is deteriorated. This phenomenon can not be identified by a cost function, which only considers placement area and total wire length. Therefore, we would like to introduce the necessity of considering boundary constraint for the modules with input or output ports in symmetry islands. Based on ASF-B* tree [3], we explore the feasible conditions for 1D and 2D symmetry islands to meet this constraint. Further, a procedure is presented to maintain the easibility for each ASF-B* tree after perturbation. Experimental results show that our approach guarantees the boundary property for the modules with input or output ports in symmetry islands.

Original languageEnglish
Title of host publicationProceedings of the 47th Design Automation Conference, DAC '10
Number of pages6
Publication statusPublished - 2010 Sep 7
Event47th Design Automation Conference, DAC '10 - Anaheim, CA, United States
Duration: 2010 Jun 132010 Jun 18

Publication series

NameProceedings - Design Automation Conference
ISSN (Print)0738-100X


Other47th Design Automation Conference, DAC '10
CountryUnited States
CityAnaheim, CA

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modelling and Simulation

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