Performance-driven analog placement considering monotonic current paths

Po Hsun Wu; Mark Po Hung Lin; Yang Ru Chen; Bing Shiun Chou; Tung Chieh Chen; Tsung Yi Ho; Bin Da Liu

doi:10.1145/2429384.2429516

Performance-driven analog placement considering monotonic current paths

Po Hsun Wu, Mark Po Hung Lin, Yang Ru Chen, Bing Shiun Chou, Tung Chieh Chen, Tsung Yi Ho, Bin Da Liu

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

24 Citations (Scopus)

Abstract

Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

Original language	English
Article number	6386735
Pages (from-to)	613-619
Number of pages	7
Journal	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
DOIs	https://doi.org/10.1145/2429384.2429516
Publication status	Published - 2012
Event	2012 30th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012 - San Jose, CA, United States Duration: 2012 Nov 5 → 2012 Nov 8

All Science Journal Classification (ASJC) codes

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

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10.1145/2429384.2429516

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title = "Performance-driven analog placement considering monotonic current paths",

abstract = "Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.",

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AU - Wu, Po Hsun

AU - Lin, Mark Po Hung

AU - Chen, Yang Ru

AU - Chou, Bing Shiun

AU - Chen, Tung Chieh

AU - Ho, Tsung Yi

AU - Liu, Bin Da

PY - 2012

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N2 - Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

AB - Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact on circuit performance, and derives new problem formulation and algorithms to find placement solutions with monotonic current paths. Experimental results show that the proposed formulation and algorithms can generate compact layouts resulting in the even better circuit performance after performing post-layout simulation.

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JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

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Performance-driven analog placement considering monotonic current paths

Abstract

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