Performance-driven placement for dynamically reconfigurable FPGAs

Guang Ming Wu, Jai-Ming Lin, Yao Wen Chang

Research output: Contribution to journalArticle

Abstract

In this article, we introduce a new placement problem motivated by the Dynamically Reconfigurable FPGA (DRFPGA) architectures. Unlike traditional placement, the problem for DRFPGAs must consider the precedence constraints among logic components. For the placement, we develop an effective metric that can consider wirelength, register requirement, and power consumption simultaneously. With the considerations of the new metric and the precedence constraints, we then present a three-stage scheme of partitioning, initial placement generation, and placement refinement to solve the new placement problem. Experimental results show that our placement scheme with the new metric achieves respective improvements of 17.2, 27.0, and 35.9% in wirelength, the number of registers, and power consumption requirements, compared with the list scheduling method.

Original languageEnglish
Pages (from-to)628-642
Number of pages15
JournalACM Transactions on Design Automation of Electronic Systems
Volume7
Issue number4
DOIs
Publication statusPublished - 2002 Oct 1

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Field programmable gate arrays (FPGA)
Electric power utilization
Scheduling

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

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Performance-driven placement for dynamically reconfigurable FPGAs. / Wu, Guang Ming; Lin, Jai-Ming; Chang, Yao Wen.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 7, No. 4, 01.10.2002, p. 628-642.

Research output: Contribution to journalArticle

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