Abstract
Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way, memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. In this paper, we study the design strategy for cache depot that (1) enhances the network interface of each node to include a depot cache which stores those extra memory blocks for other nodes, and (2) employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together, the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS |
| Editors | C.N. Chen, L.M. Ni |
| Publisher | IEEE Comp Soc |
| Pages | 519-526 |
| Number of pages | 8 |
| Publication status | Published - 1998 |
| Event | Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS - Tainan, China Duration: 1998 Dec 14 → 1998 Dec 16 |
Other
| Other | Proceedings of the 1998 International Conference on Parallel and Distributed Systems, ICPADS |
|---|---|
| City | Tainan, China |
| Period | 98-12-14 → 98-12-16 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
Cite this
}
Performance evaluation of cache depot on CC-NUMA multiprocessors. / Hsiao, Hung-Chang; King, Chung Ta.
Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS. ed. / C.N. Chen; L.M. Ni. IEEE Comp Soc, 1998. p. 519-526.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - Performance evaluation of cache depot on CC-NUMA multiprocessors
AU - Hsiao, Hung-Chang
AU - King, Chung Ta
PY - 1998
Y1 - 1998
N2 - Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way, memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. In this paper, we study the design strategy for cache depot that (1) enhances the network interface of each node to include a depot cache which stores those extra memory blocks for other nodes, and (2) employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together, the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.
AB - Cache depot is a performance enhancement technique on cache-coherent non-uniform memory access (CC-NUMA) multiprocessors, in which nodes in the system store extra memory blocks on behalf of other nodes. In this way, memory requests from a node can be satisfied by nearby depot nodes without going all the way to the home node. This not only reduces memory access latency and network traffic, but also spreads the network load more evenly. In this paper, we study the design strategy for cache depot that (1) enhances the network interface of each node to include a depot cache which stores those extra memory blocks for other nodes, and (2) employs a new multicast routing scheme, which is called the multi-hop worms and works cooperatively with depot caches, to transmit coherence messages. By considering message routing and depot caches together, the design concept can be applied even to those CC-NUMA systems that have a non-hierarchical, scalable interconnection network. We have developed an execution-driven simulator to evaluate the effectiveness of the design strategy. Performance results from using four SPLASH-2 benchmarks show that the design strategy improves the performance of the CC-NUMA multiprocessor by 11% to 21%. We have also studied in depth various factors which affect the performance of cache depot.
UR - http://www.scopus.com/inward/record.url?scp=0032300644&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0032300644&partnerID=8YFLogxK
M3 - Conference contribution
SP - 519
EP - 526
BT - Proceedings of the Internatoinal Conference on Parallel and Distributed Systems - ICPADS
A2 - Chen, C.N.
A2 - Ni, L.M.
PB - IEEE Comp Soc
ER -