Performance evaluation of priority buffer management in ATM switches

Hui Tang Lin, Herman D. Hughes

Research output: Contribution to journalArticlepeer-review


In regard to switch design, the location of the buffer has a great impact on switch performance and transmission latency. Most research to date deals with a single buffer for each input1-3 or output port1-6. However, the real-time transmission may suffer long queuing delay because of the single First-In-First-Out (FIFO) queuing scheme. Furthermore, users cannot take advantage of available bandwidth when the utilization of the network is low, since they cannot exceed their initially allocated bandwidth. This paper presents a switching architecture to study the issue of multimedia traffic on ATM networks with varying priorities and time requirements. It also provides a methodology which allows unassigned bandwidth to be used and this is shown to enhance the network utilization. Our model is based on nonblocking switches with multiple output buffers for different priority traffic at each output port. Window selection, typically used to solve the problem of Head of Line (HOL) blocking in an input buffer switch, is applied in this study to give priority to real-time traffic. By combining window selection and multiple output buffers, the various requirements of QoS for different traffic are investigated. It is shown that this hybrid scheme can be used to increase the network utilization without causing an unacceptable delay to the real-time green cell. Simulation and analytical models are used to study the traffic delay.

Original languageEnglish
Pages (from-to)387-393
Number of pages7
JournalComputer Systems Science and Engineering
Issue number6
Publication statusPublished - 1997 Nov

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Theoretical Computer Science
  • General Computer Science


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