Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

Meng Yen Wu, Meng Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

Original languageEnglish
Title of host publicationProceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
PublisherIEEE Computer Society
Pages169-172
Number of pages4
ISBN (Electronic)9781509012138
DOIs
Publication statusPublished - 2016 May 25
Event17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, United States
Duration: 2016 Mar 152016 Mar 16

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2016-May
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Other

Other17th International Symposium on Quality Electronic Design, ISQED 2016
CountryUnited States
CitySanta Clara
Period16-03-1516-03-16

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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