Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

Meng Yen Wu; Meng Hsueh Chiang

doi:10.1109/ISQED.2016.7479195

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

Meng Yen Wu, Meng Hsueh Chiang

Doctoral Degree Program on Nano-Integrated-Circuit Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

Original language	English
Title of host publication	Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
Publisher	IEEE Computer Society
Pages	169-172
Number of pages	4
ISBN (Electronic)	9781509012138
DOIs	https://doi.org/10.1109/ISQED.2016.7479195
Publication status	Published - 2016 May 25
Event	17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, United States Duration: 2016 Mar 15 → 2016 Mar 16

Publication series

Name	Proceedings - International Symposium on Quality Electronic Design, ISQED
Volume	2016-May
ISSN (Print)	1948-3287
ISSN (Electronic)	1948-3295

Other

Other	17th International Symposium on Quality Electronic Design, ISQED 2016
Country/Territory	United States
City	Santa Clara
Period	16-03-15 → 16-03-16

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

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10.1109/ISQED.2016.7479195

Cite this

Wu, M. Y., & Chiang, M. H. (2016). Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. In Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016 (pp. 169-172). Article 7479195 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2016-May). IEEE Computer Society. https://doi.org/10.1109/ISQED.2016.7479195

@inproceedings{58a6650d4a1e4ec5b32cc2f839655ab4,

title = "Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes",

abstract = "Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.",

author = "Wu, {Meng Yen} and Chiang, {Meng Hsueh}",

note = "Publisher Copyright: {\textcopyright} 2016 IEEE.; 17th International Symposium on Quality Electronic Design, ISQED 2016 ; Conference date: 15-03-2016 Through 16-03-2016",

year = "2016",

month = may,

day = "25",

doi = "10.1109/ISQED.2016.7479195",

language = "English",

series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",

publisher = "IEEE Computer Society",

pages = "169--172",

booktitle = "Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016",

address = "United States",

}

Wu, MY & Chiang, MH 2016, Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. in Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016., 7479195, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2016-May, IEEE Computer Society, pp. 169-172, 17th International Symposium on Quality Electronic Design, ISQED 2016, Santa Clara, United States, 16-03-15. https://doi.org/10.1109/ISQED.2016.7479195

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes. / Wu, Meng Yen; Chiang, Meng Hsueh.
Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016. IEEE Computer Society, 2016. p. 169-172 7479195 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2016-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

AU - Wu, Meng Yen

AU - Chiang, Meng Hsueh

PY - 2016/5/25

Y1 - 2016/5/25

N2 - Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

AB - Performance evaluation of stacked gate-all-around (GAA) MOSFETs on device scaling and performance benchmark against FinFETs based on scale length are presented. While stacked GAA technique provides higher current (per pitch), FinFET counterpart shows its advantage in intrinsic gate delay. Such advantage becomes even more significant toward smaller technology node. By adjusting the aspect ratio of GAA devices based on same scale length, the thinner rectangular GAA case allows more stacked layers than the square case at the same total height and hence provides higher current. However, comparable intrinsic speeds are predicted for both cases.

UR - http://www.scopus.com/inward/record.url?scp=84973862299&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84973862299&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2016.7479195

DO - 10.1109/ISQED.2016.7479195

M3 - Conference contribution

AN - SCOPUS:84973862299

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 169

EP - 172

BT - Proceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016

PB - IEEE Computer Society

T2 - 17th International Symposium on Quality Electronic Design, ISQED 2016

Y2 - 15 March 2016 through 16 March 2016

ER -

Performance evaluation of stacked gate-all-around MOSFETs at 7 and 10 nm technology nodes

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