Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors

Chun Yu Chen, Jyi Tsong Lin, Meng Hsueh Chiang

Research output: Contribution to journalArticle

4 Citations (Scopus)


A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22 nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this work shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension. The nanowire diameter designed at two thirds of gate length minus three times gate oxide thickness is shown to achieve good control of short-channel effects.

Original languageEnglish
Pages (from-to)57-62
Number of pages6
JournalSolid-State Electronics
Publication statusPublished - 2014 Feb 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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