Perspective of tunnel-FET for future low-power technology nodes

A. S. Verhulst, D. Verreck, Q. Smets, K. H. Kao, M. Van De Put, R. Rooyackers, B. Sorée, A. Vandooren, K. De Meyer, G. Groeseneken, M. M. Heyns, A. Mocuta, N. Collaert, A. V.Y. Thean

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Theoretically, confined heterostructure p(-n)-i-n (n(-p)-i-p) TFETs are promising candidates for future low-power applications, with n-TFET outperforming p-TFET. An optimal body thickness of about 10nm is predicted for Ga0.5As0.5Sb-In0.53Ga0.47As n-TFET with I60=20μA/μm. For p-TFETs, stronger confinement may be required to avoid tunneling to the heavy-hole band. An unexploited domain is the insertion of thin heterostructure slabs offering a locally reduced dielectric constant, enhancing both SS and Ion.

Original languageEnglish
Title of host publication2014 IEEE International Electron Devices Meeting, IEDM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages30.2.1-30.2.4
EditionFebruary
ISBN (Electronic)9781479980017
DOIs
Publication statusPublished - 2015 Feb 20
Event2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
Duration: 2014 Dec 152014 Dec 17

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
NumberFebruary
Volume2015-February
ISSN (Print)0163-1918

Other

Other2014 60th IEEE International Electron Devices Meeting, IEDM 2014
CountryUnited States
CitySan Francisco
Period14-12-1514-12-17

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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