Perspective of tunnel-FET for future low-power technology nodes

A. S. Verhulst, D. Verreck, Q. Smets, Kuo-Hsing Kao, M. Van De Put, R. Rooyackers, B. Sorée, A. Vandooren, K. De Meyer, G. Groeseneken, M. M. Heyns, A. Mocuta, N. Collaert, A. V.Y. Thean

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

Theoretically, confined heterostructure p(-n)-i-n (n(-p)-i-p) TFETs are promising candidates for future low-power applications, with n-TFET outperforming p-TFET. An optimal body thickness of about 10nm is predicted for Ga0.5As0.5Sb-In0.53Ga0.47As n-TFET with I60=20μA/μm. For p-TFETs, stronger confinement may be required to avoid tunneling to the heavy-hole band. An unexploited domain is the insertion of thin heterostructure slabs offering a locally reduced dielectric constant, enhancing both SS and Ion.

Original languageEnglish
Title of host publication2014 IEEE International Electron Devices Meeting, IEDM 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages30.2.1-30.2.4
EditionFebruary
ISBN (Electronic)9781479980017
DOIs
Publication statusPublished - 2015 Feb 20
Event2014 60th IEEE International Electron Devices Meeting, IEDM 2014 - San Francisco, United States
Duration: 2014 Dec 152014 Dec 17

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
NumberFebruary
Volume2015-February
ISSN (Print)0163-1918

Other

Other2014 60th IEEE International Electron Devices Meeting, IEDM 2014
CountryUnited States
CitySan Francisco
Period14-12-1514-12-17

Fingerprint

Field effect transistors
Heterojunctions
tunnels
insertion
Tunnels
slabs
field effect transistors
permittivity
Permittivity

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Cite this

Verhulst, A. S., Verreck, D., Smets, Q., Kao, K-H., Van De Put, M., Rooyackers, R., ... Thean, A. V. Y. (2015). Perspective of tunnel-FET for future low-power technology nodes. In 2014 IEEE International Electron Devices Meeting, IEDM 2014 (February ed., pp. 30.2.1-30.2.4). [7047140] (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2014.7047140
Verhulst, A. S. ; Verreck, D. ; Smets, Q. ; Kao, Kuo-Hsing ; Van De Put, M. ; Rooyackers, R. ; Sorée, B. ; Vandooren, A. ; De Meyer, K. ; Groeseneken, G. ; Heyns, M. M. ; Mocuta, A. ; Collaert, N. ; Thean, A. V.Y. / Perspective of tunnel-FET for future low-power technology nodes. 2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 30.2.1-30.2.4 (Technical Digest - International Electron Devices Meeting, IEDM; February).
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Verhulst, AS, Verreck, D, Smets, Q, Kao, K-H, Van De Put, M, Rooyackers, R, Sorée, B, Vandooren, A, De Meyer, K, Groeseneken, G, Heyns, MM, Mocuta, A, Collaert, N & Thean, AVY 2015, Perspective of tunnel-FET for future low-power technology nodes. in 2014 IEEE International Electron Devices Meeting, IEDM 2014. February edn, 7047140, Technical Digest - International Electron Devices Meeting, IEDM, no. February, vol. 2015-February, Institute of Electrical and Electronics Engineers Inc., pp. 30.2.1-30.2.4, 2014 60th IEEE International Electron Devices Meeting, IEDM 2014, San Francisco, United States, 14-12-15. https://doi.org/10.1109/IEDM.2014.7047140

Perspective of tunnel-FET for future low-power technology nodes. / Verhulst, A. S.; Verreck, D.; Smets, Q.; Kao, Kuo-Hsing; Van De Put, M.; Rooyackers, R.; Sorée, B.; Vandooren, A.; De Meyer, K.; Groeseneken, G.; Heyns, M. M.; Mocuta, A.; Collaert, N.; Thean, A. V.Y.

2014 IEEE International Electron Devices Meeting, IEDM 2014. February. ed. Institute of Electrical and Electronics Engineers Inc., 2015. p. 30.2.1-30.2.4 7047140 (Technical Digest - International Electron Devices Meeting, IEDM; Vol. 2015-February, No. February).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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AU - Groeseneken, G.

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AB - Theoretically, confined heterostructure p(-n)-i-n (n(-p)-i-p) TFETs are promising candidates for future low-power applications, with n-TFET outperforming p-TFET. An optimal body thickness of about 10nm is predicted for Ga0.5As0.5Sb-In0.53Ga0.47As n-TFET with I60=20μA/μm. For p-TFETs, stronger confinement may be required to avoid tunneling to the heavy-hole band. An unexploited domain is the insertion of thin heterostructure slabs offering a locally reduced dielectric constant, enhancing both SS and Ion.

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Verhulst AS, Verreck D, Smets Q, Kao K-H, Van De Put M, Rooyackers R et al. Perspective of tunnel-FET for future low-power technology nodes. In 2014 IEEE International Electron Devices Meeting, IEDM 2014. February ed. Institute of Electrical and Electronics Engineers Inc. 2015. p. 30.2.1-30.2.4. 7047140. (Technical Digest - International Electron Devices Meeting, IEDM; February). https://doi.org/10.1109/IEDM.2014.7047140