TY - JOUR
T1 - Phase characteristic and segregation related with corrosion on hypereutectic Sn–Bi solder under thermal storage and cycling corrosion test
AU - Ho, Ching Yuan
AU - Lo, Yi Chun
N1 - Funding Information:
High performance, miniaturization and multifunction of electronic products are accompanying with 5G related high technologies applications, fast data transport, cheaper cost, and excellent reliability. However, the Moore's law for device miniaturization has near ending meaning that technique to shrink transistor architecture on VLSI process is suffering from physical limit and process tolerance. Therefore, the IC process window gets narrow and difficult to obtain high yield and reliability [1,2]. To overcome the bottleneck, 3D package technologies instead of the part of chips function are carrying out and compensate the critical shrinkage problems on VLSI process. In the last decade, IC package evolved from two-dimensions package to three-dimension, different functions of products were assembled on same chip (SOC) but these products such as analogies and digitals were not easy to integrate through the SoC process, or if these functions were barely integrated together to produce SoCs, it was too costly. The advantage of SIP can assemble multiple chips or heterogeneous integration in a single package to build more complex system, but wire bonding interconnection is main issue when the number of stacked chips increases, longer length of wire bonding is required for the upper layer of chips, which also affects the performance of the entire system. Recently, several new 3D IC processes have been reported responding to the demand of high-frequency, versatile functions and chip volumetric reduction. For example, through-silicon-via method connects die to die or fan-out wafer level package use RDL to connect different dies [3,4]. The redistributed line (RDL) contained in the interposer proposes the interconnection function between dies and together with solder joints to form the stacking chips, however the effects of thermal budget on solder properties are serious problems. For example, as the first level of solder joints should have the highest melting point which will not be melted during the processing of the second level solder joints. Moreover, the interposer with less than 50 μm thickness and polymer substrate facilitate to generate undesirable phenomenon on packaging technology. Thermal stability is another concern for substrate warpage because large surface and huge different of CTE between the thin interposer and silicon wafer-level package (WLP) or glass panel-level package (PLP) [5,6]. Recently, solder joints instead of wire bonding provide the mechanical support and electrical/signal connection between the chips and substrates, however, the reliability of IC package is critical to thermal process because the microstructure of solder alloys and interfacial intermetallic compound (IMC) layers significantly affect the overall IC performance. When the chips become more functionalized, the SiP technology, Fan-out WLP or Fan-out PLP, which chips are connected horizontal and vertical to reduce package size and raise up signal transmission speed, and more universal. Unfortunately, solder reflow temperature always leads to substrate warpage and results in poor yield and reliability issues [7,8].
Publisher Copyright:
© 2023 Elsevier B.V.
PY - 2023/3/1
Y1 - 2023/3/1
N2 - Hypereutectic Sn-58%wt Bi solders were synthesized to observe phase change, corrosion and electrical endurance by various thermal storages. Initially, Cu6Sn5 IMC layer thickness is linear growth by Sn reacting with Cu joint, following, the Cu3Sn IMC starts to grow when the Cu6Sn5 is thicker enough to obstruct Cu inter-diffusing into solder. The segregation of Bi concentration gradient in eutectic phase is mitigated by homogenization treatment but corrosion resistance is deteriorated. Lump shape of SnO2 corrosive byproduct is initially observed, then the flower shape of Bi3O2 is found after Sn corroding completely. Moreover, phase change of solder related with current endurance is studied.
AB - Hypereutectic Sn-58%wt Bi solders were synthesized to observe phase change, corrosion and electrical endurance by various thermal storages. Initially, Cu6Sn5 IMC layer thickness is linear growth by Sn reacting with Cu joint, following, the Cu3Sn IMC starts to grow when the Cu6Sn5 is thicker enough to obstruct Cu inter-diffusing into solder. The segregation of Bi concentration gradient in eutectic phase is mitigated by homogenization treatment but corrosion resistance is deteriorated. Lump shape of SnO2 corrosive byproduct is initially observed, then the flower shape of Bi3O2 is found after Sn corroding completely. Moreover, phase change of solder related with current endurance is studied.
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U2 - 10.1016/j.matchemphys.2023.127386
DO - 10.1016/j.matchemphys.2023.127386
M3 - Article
AN - SCOPUS:85146713102
SN - 0254-0584
VL - 297
JO - Materials Chemistry and Physics
JF - Materials Chemistry and Physics
M1 - 127386
ER -