In the SiGe strain engineering on pMOS, the reactive ion etching (RIE) is using to prepare a Si recess, and then use epitaxial growth to form SiGe strain liner on both sides of poly gate. In the dense line CMOS, the shrunk Si recess dimension make it steeper and introduces the challenge to remove the post etch polymer residue. It is investigated that residual polymer on steep side wall of channel will prohibit the following Selective Epitaxial Growth of SiGe (SEG) and directly impact the yield. An enhanced chemical process has proposed for surface preparation and the processes are explored to determine the clean efficiency of plasma modified polymer residue. The developed process is capable to eradicate residual polymer defect on both isolated and dense layout structure of 45nm pMOS and resulted 3~10% physical yield improvement.