Pipelined architecture of fast modular multiplication for RSA cryptography

Jia Lin Sheu, Ming-Der Shieh, Chien Hsing Wu, Ming Hwa Sheu

Research output: Contribution to journalConference articlepeer-review

7 Citations (Scopus)


In this paper, a fast algorithm with its corresponding VLSI architecture is proposed to speed up the modular multiplication with a large modulus. By partitioning the operand (multiplier) into several equal-sized segments, and performing the multiplication and residue calculation of each segment in a pipelined fashion, a performance improvement can be achieved by using our algorithm compared with previous work. We also show an efficient procedure to accelerate the residue calculation and use carry-save addition to implement the architecture such that the critical path is independent of the size of the modulus. Therefore, the resulting architecture and implementation are very suitable to be applied to the high-speed RSA cryptosystem and can be easily implemented in VLSI technology.

Original languageEnglish
Pages (from-to)121-124
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 1998 Jan 1
EventProceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6) - Monterey, CA, USA
Duration: 1998 May 311998 Jun 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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