Pipelined VLSI with module structure design for discrete wavelet transforms

Ming Hwa Sheu; Shun Fa Cheng; Ming Der Shieh

Pipelined VLSI with module structure design for discrete wavelet transforms

Ming Hwa Sheu, Shun Fa Cheng, Ming Der Shieh

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.

Original language	English
Pages (from-to)	352-355
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	4
Publication status	Published - 1996 Jan 1
Event	Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: 1996 May 12 → 1996 May 15

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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title = "Pipelined VLSI with module structure design for discrete wavelet transforms",

abstract = "This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.",

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AU - Cheng, Shun Fa

AU - Shieh, Ming Der

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N2 - This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.

AB - This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.

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VL - 4

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EP - 355

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

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T2 - Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4)

Y2 - 12 May 1996 through 15 May 1996

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