This paper presents an efficient pipelined VLSI architecture for computing the Discrete Wavelet Transform. The features of the architecture are 1) lower hardware cost, 2) shorter latency, 3) simplex control, 4) regular structure for VLSI implementation and 5) higher output throughput rate. Under considering the precision of the transformed data, the architecture has been done accuracy analysis to determine the appropriate bit-width for fitting the hardware executions. Finally, all components in the architecture are well designed and simulated based on the accuracy requirement.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1996 Jan 1|
|Event||Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA|
Duration: 1996 May 12 → 1996 May 15
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering