PLL control scheme for the electronic ballast with a current-equalization network

Ray Lee Lin, Chien Hsin Wen

Research output: Contribution to journalArticlepeer-review

9 Citations (Scopus)

Abstract

This paper proposes a phase-locked loop (PLL) control scheme for the electronic ballast with a current-equalization network. The PLL control scheme involves detecting the phase signals of both the resonant-tank input voltage and the two leakage-inductor terminals in the transformer; then the operating frequency of the circuit continuously tracks the resonant frequency as a reference frequency. Based on the tracked reference frequency, the required voltage gain of the resonant tank is regulated by offsetting the operating frequency. Consequently, the operating frequency is lower than the resonant frequency to ensure the zero-voltage-switching (ZVS) condition for less turn-on switching losses on the switches. This paper presents the analysis of the proposed PLL control scheme. Finally, the current-equalizing ability in the dimming range is demonstrated by experiments in order to validate and demonstrate the performance and feasibility of the proposed circuit.

Original languageEnglish
Pages (from-to)160-169
Number of pages10
JournalIEEE/OSA Journal of Display Technology
Volume2
Issue number2
DOIs
Publication statusPublished - 2006 Jun 1

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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