Power consumption ameliorated for integrated gate driver circuit with low frequency clock

Chih Lung Lin, Chun Da Tu, Chia Che Hung, Mao Hsun Cheng, Chia En Wu, Yung Chih Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a novel low power consumption gate driver circuit with 12 TFTs and one capacitor which is made by hydrogenated amorphous silicon technology. The pull-down structure can not only prevent the floating of gate lines, but also suppress the threshold voltage shift of a-Si:H TFTs. According to the measurement results, the proposed gate driver circuit can be operated stably more than 10 days at high temperature (T = 100°C). Furthermore, the power consumption of the proposed gate driver circuit can be reduced 52.6% compared to the previously proposed gate driver circuit.

Original languageEnglish
Title of host publication49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
Pages1285-1287
Number of pages3
Publication statusPublished - 2011 Dec 1
Event49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011 - Los Angeles, CA, United States
Duration: 2011 May 152011 May 20

Publication series

Name49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
Volume3

Other

Other49th Annual SID Symposium, Seminar, and Exhibition 2011, Display Week 2011
Country/TerritoryUnited States
CityLos Angeles, CA
Period11-05-1511-05-20

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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