Power-effective ROM-less DDFS Design Approach with High SFDR Performance

Chua Chin Wang, Nanang Sulistiyanto, Hsiang Yu Shih, Yu Cheng Lin, Wei Wang

Research output: Contribution to journalArticle

Abstract

A ROM-less direct digital frequency synthesizer (DDFS) design approach based on interpolation schemes is proposed in this work. Besides achieving higher SFDR (spurious free dynamic range) and faster clock rate, detailed power estimation approach based on switching activity analysis of each logic sub-blocks is presented to explore the optimal solution. The parabolic equations with proper selection of coefficients and pipeline structure are utilized to enhance SFDR. A ROM-less DDFS using the proposed design approach is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.

Original languageEnglish
Pages (from-to)213-224
Number of pages12
JournalJournal of Signal Processing Systems
Volume92
Issue number2
DOIs
Publication statusPublished - 2020 Feb 1

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All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modelling and Simulation
  • Hardware and Architecture

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