Power-efficient and scalable load/store queue design via address compression

Yi Ying Tsai, Chia Jung Hsu, Chung-Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes an address compression technique for load/store queue (LSQ) to improve the scalability and power efficiency. A load/store queue (LSQ) typically needs a fullyassociative CAM structure to search the address for collision and consequently poses scalability challenges of power consumption and area cost. Using the proposed approach, the LSQ can reduce the area cost ranging from 32% to 66% and power consumption ranging from 38% to 71%, depending on the compression parameter. The approach can provide 3.08% overall processor energy reduction and causes only 0.22% performance loss at an optimal configuration.

Original languageEnglish
Title of host publicationProceedings of the 23rd Annual ACM Symposium on Applied Computing, SAC'08
Pages1523-1527
Number of pages5
DOIs
Publication statusPublished - 2008 Dec 1
Event23rd Annual ACM Symposium on Applied Computing, SAC'08 - Fortaleza, Ceara, Brazil
Duration: 2008 Mar 162008 Mar 20

Publication series

NameProceedings of the ACM Symposium on Applied Computing

Other

Other23rd Annual ACM Symposium on Applied Computing, SAC'08
CountryBrazil
CityFortaleza, Ceara
Period08-03-1608-03-20

All Science Journal Classification (ASJC) codes

  • Software

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