Pragmatic study of the nanowire FETs with nonideal gate structures

Jyi Tsong Lin, Chun Yu Chen, Meng-Hsueh Chiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire,are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.

Original languageEnglish
Title of host publication2010 Silicon Nanoelectronics Workshop, SNW 2010
DOIs
Publication statusPublished - 2010 Oct 22
Event2010 15th Silicon Nanoelectronics Workshop, SNW 2010 - Honolulu, HI, United States
Duration: 2010 Jun 132010 Jun 14

Publication series

Name2010 Silicon Nanoelectronics Workshop, SNW 2010

Other

Other2010 15th Silicon Nanoelectronics Workshop, SNW 2010
CountryUnited States
CityHonolulu, HI
Period10-06-1310-06-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Pragmatic study of the nanowire FETs with nonideal gate structures'. Together they form a unique fingerprint.

  • Cite this

    Lin, J. T., Chen, C. Y., & Chiang, M-H. (2010). Pragmatic study of the nanowire FETs with nonideal gate structures. In 2010 Silicon Nanoelectronics Workshop, SNW 2010 [5562568] (2010 Silicon Nanoelectronics Workshop, SNW 2010). https://doi.org/10.1109/SNW.2010.5562568