TY - GEN
T1 - Pragmatic study of the nanowire FETs with nonideal gate structures
AU - Lin, Jyi Tsong
AU - Chen, Chun Yu
AU - Chiang, Meng Hsueh
PY - 2010
Y1 - 2010
N2 - Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire,are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.
AB - Device characteristics of the nanowire FETs with nonideal gate structures, such as nonuniform gate oxide and elliptic wire,are investigated using 3D numerical simulation. As the nonideal nanowire cases show acceptable device characteristics and still maintain good performance projection, various nanowires FETs are thus flexible for manufacturing. By simply changing the wire diameter from 10 nm to 7 nm at the 25 nm technology node, 22% improvement in gate delay is predicted.
UR - https://www.scopus.com/pages/publications/77958013452
UR - https://www.scopus.com/pages/publications/77958013452#tab=citedBy
U2 - 10.1109/SNW.2010.5562568
DO - 10.1109/SNW.2010.5562568
M3 - Conference contribution
AN - SCOPUS:77958013452
SN - 9781424477272
T3 - 2010 Silicon Nanoelectronics Workshop, SNW 2010
BT - 2010 Silicon Nanoelectronics Workshop, SNW 2010
T2 - 2010 15th Silicon Nanoelectronics Workshop, SNW 2010
Y2 - 13 June 2010 through 14 June 2010
ER -