Process and Structure Considerations for the Post FinFET Era

Chun Jung Su, Po Jung Sung, Kuo Hsing Kao, Yao Jen Lee, Wen Fa Wu, Wen Kuan Yeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

Original languageEnglish
Title of host publication2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages13-14
Number of pages2
ISBN (Electronic)9781728197357
DOIs
Publication statusPublished - 2020 Jun
Event2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States
Duration: 2020 Jun 132020 Jun 14

Publication series

Name2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
CountryUnited States
CityHonolulu
Period20-06-1320-06-14

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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