Process and Structure Considerations for the Post FinFET Era

Chun Jung Su; Po Jung Sung; Kuo Hsing Kao; Yao Jen Lee; Wen Fa Wu; Wen Kuan Yeh

doi:10.1109/SNW50361.2020.9131422

Process and Structure Considerations for the Post FinFET Era

Chun Jung Su, Po Jung Sung, Kuo Hsing Kao, Yao Jen Lee, Wen Fa Wu, Wen Kuan Yeh

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.

Original language	English
Title of host publication	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	13-14
Number of pages	2
ISBN (Electronic)	9781728197357
DOIs	https://doi.org/10.1109/SNW50361.2020.9131422
Publication status	Published - 2020 Jun
Event	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 - Honolulu, United States Duration: 2020 Jun 13 → 2020 Jun 14

Publication series

Name	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020

Conference

Conference	2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020
Country/Territory	United States
City	Honolulu
Period	20-06-13 → 20-06-14

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/SNW50361.2020.9131422

Cite this

Su, C. J., Sung, P. J., Kao, K. H., Lee, Y. J., Wu, W. F., & Yeh, W. K. (2020). Process and Structure Considerations for the Post FinFET Era. In 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 (pp. 13-14). Article 9131422 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SNW50361.2020.9131422

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title = "Process and Structure Considerations for the Post FinFET Era",

abstract = "Evolution of transistor structures, from planar, fin to gate-all-around (GAA) nanowire (NW)/nanosheet (NS), enables consecutive device scaling and performance boost. To further enhance the drive current per footprint, a vertically stacked configuration compatible with current CMOS technology may be a promising approach for extending Moore's Law. In this paper, we review the recent status of stacked FET architectures and beyond, as well as pointing out the challenges and perspectives.",

author = "Su, {Chun Jung} and Sung, {Po Jung} and Kao, {Kuo Hsing} and Lee, {Yao Jen} and Wu, {Wen Fa} and Yeh, {Wen Kuan}",

note = "Funding Information: This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST-107-2628-E-492-001-MY3, 109-2923-E-492-002-MY3, 109-2639-E-009-001, 109-2634-F-009-029 and 109-2636-E-006-004. Also in part by financially supported by the “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE) in Taiwan. The authors would also like to thank the support of Hitachi High-Technologies Corp. Publisher Copyright: {\textcopyright} 2020 IEEE.; 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020 ; Conference date: 13-06-2020 Through 14-06-2020",

year = "2020",

month = jun,

doi = "10.1109/SNW50361.2020.9131422",

language = "English",

series = "2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020",

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Su, CJ, Sung, PJ, Kao, KH, Lee, YJ, Wu, WF & Yeh, WK 2020, Process and Structure Considerations for the Post FinFET Era. in 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020., 9131422, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Institute of Electrical and Electronics Engineers Inc., pp. 13-14, 2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020, Honolulu, United States, 20-06-13. https://doi.org/10.1109/SNW50361.2020.9131422

Process and Structure Considerations for the Post FinFET Era. / Su, Chun Jung; Sung, Po Jung; Kao, Kuo Hsing et al.
2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 13-14 9131422 (2020 IEEE Silicon Nanoelectronics Workshop, SNW 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST-107-2628-E-492-001-MY3, 109-2923-E-492-002-MY3, 109-2639-E-009-001, 109-2634-F-009-029 and 109-2636-E-006-004. Also in part by financially supported by the “Center for the Semiconductor Technology Research” from The Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education (MOE) in Taiwan. The authors would also like to thank the support of Hitachi High-Technologies Corp. Publisher Copyright: © 2020 IEEE.

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Process and Structure Considerations for the Post FinFET Era

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