Abstract
In this paper, we propose a parallel and programmable VLC decoder which includes the arithmetic representation of codewords, codeword regularity, and its hardware configuration. With the proposed hardware configuration, the parallel VLC decoder is faster and with less memory than the traditional decoder. Furthermore, the programmable VLC decoder, which can decode more codewords in one clock, can be devised by extending the parallel concept.
Original language | English |
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Pages (from-to) | 448-454 |
Number of pages | 7 |
Journal | IEEE Transactions on Consumer Electronics |
Volume | 39 |
Issue number | 3 |
DOIs | |
Publication status | Published - 1993 Aug |
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering