TY - GEN
T1 - Programmable pacing channel with a fully on-chip LDO regulator for cardiac pacemaker
AU - Cheng, Chih Jen
AU - Wu, Chung Jui
AU - Lee, Shuenn-Yuh
PY - 2008/12/1
Y1 - 2008/12/1
N2 - A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-μm CMOS technology, consuming total power of 1.29 μW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a powersupply rejection ratio (PSRR) of -30 dB with the output ripple of 570 μVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 μA, LDO yields a line regulation that is less than 3% deviation.
AB - A novel dual-voltage pacing system for implant pacemaker is presented in this paper. In order to reduce supply voltage ripple and diminish process variation imposed on the divided-resistor, a fully on-chip low-dropout (LDO) regulator is proposed. Meanwhile, the adjustable pacing circuit together with a sense feedback is employed to deliver electrical stimuli of 16-step amplitudes to induce cardiac contraction. The pacing circuit with a LDO regulator was fabricated in TSMC 0.35-μm CMOS technology, consuming total power of 1.29 μW including 185 nA of ground current in 1.2-V LDO and having a power consumption of 30 nW in the 1-V pacing step controller. Experimental results demonstrate that the proposed LDO regulator features a powersupply rejection ratio (PSRR) of -30 dB with the output ripple of 570 μVpp under the input sinusoidal wave of 19.6 mVpp. Even with the load current up to 10 μA, LDO yields a line regulation that is less than 3% deviation.
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U2 - 10.1109/ASSCC.2008.4708783
DO - 10.1109/ASSCC.2008.4708783
M3 - Conference contribution
AN - SCOPUS:67649970878
SN - 9781424426058
T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
SP - 285
EP - 288
BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Y2 - 3 November 2008 through 5 November 2008
ER -