Programmable reference for power-aware DVS

Chun Hung Yang, Jiunn Hung Shiau, Chien Hung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper present an efficient technique and mixed-level design of programmable generating accurate reference voltage. The technique comprises a second-order error feedback Σ-Δ modulators sequence, which is then smoothed by a second-order RC filter. An FPGA-based test platform for the to-bit programmable reference is implemented for hardware realization to verify the proposed design approach. Experimental results show that the linear range of voltage is obtained from 0.4 to 3V and the step response between 0.9 and 1.2 V is equal to 1.5 μs, thus validating the functionality of the mixed-level model. Further verification is found by the experimental results being equivalent to the simulation results.

Original languageEnglish
Title of host publication2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide
Pages166-170
Number of pages5
DOIs
Publication statusPublished - 2010 Dec 1
Event2010 2nd International Symposium on Aware Computing, ISAC 2010 - Sapporo, Japan
Duration: 2010 Nov 12010 Nov 4

Publication series

Name2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide

Other

Other2010 2nd International Symposium on Aware Computing, ISAC 2010
CountryJapan
CitySapporo
Period10-11-0110-11-04

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Computer Science Applications

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  • Cite this

    Yang, C. H., Shiau, J. H., & Tsai, C. H. (2010). Programmable reference for power-aware DVS. In 2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide (pp. 166-170). [5670473] (2010 2nd International Symposium on Aware Computing, ISAC 2010 - Symposium Guide). https://doi.org/10.1109/ISAC.2010.5670473