Programmable system-on-chip for silicon prototyping

Chun Ming Huang, Chien Ming Wu, Chih Chyau Yang, Shih Lun Chen, Chi Shi Chen, Jiann Jenn Wang, Kuen Jong Lee, Chin Long Wey

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

This paper presents a programmable system-on-chip (SoC) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing a common SoC platform. In this implementation, an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03 mm2, while the area of the integrated platform is about 24.43 mm2. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13-μm CMOS generic logic process technology.

Original languageEnglish
Article number4926187
Pages (from-to)830-838
Number of pages9
JournalIEEE Transactions on Industrial Electronics
Volume58
Issue number3
DOIs
Publication statusPublished - 2011 Mar 1

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Huang, C. M., Wu, C. M., Yang, C. C., Chen, S. L., Chen, C. S., Wang, J. J., Lee, K. J., & Wey, C. L. (2011). Programmable system-on-chip for silicon prototyping. IEEE Transactions on Industrial Electronics, 58(3), 830-838. [4926187]. https://doi.org/10.1109/TIE.2009.2022075