Programmable System-on-chip (SoC) for silicon prototyping

Chun Ming Huang, Chien Ming Wu, Chih Chyau Yang, Kuen Jong Lee, Chin Long Wey

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a Programmable SoC (Systemon-chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. Results show that an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03mm2, while the area of the integrated platform is about 24.43mm2. The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13um CMOS generic logic process technology. The development of second generation MP-SoC chip is also outlined in this paper.

Original languageEnglish
Title of host publication2008 IEEE International Symposium on Industrial Electronics, ISIE 2008
Pages1976-1981
Number of pages6
DOIs
Publication statusPublished - 2008 Dec 29
Event2008 IEEE International Symposium on Industrial Electronics, ISIE 2008 - Cambridge, United Kingdom
Duration: 2008 Jun 302008 Jul 2

Publication series

NameIEEE International Symposium on Industrial Electronics

Other

Other2008 IEEE International Symposium on Industrial Electronics, ISIE 2008
CountryUnited Kingdom
CityCambridge
Period08-06-3008-07-02

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Control and Systems Engineering

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