Proteus system architecture and organization

Aran K. Somani, Craig Wittenbrink, Robert M. Haralick, Linda G. Shapiro, Jenq Neng Hwang, Chung Ho Chen, Robert Johnson, Kenneth Cooper

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Citations (Scopus)


The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use 1 M byte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling and development.

Original languageEnglish
Title of host publicationProceedings - 5th International Parallel Processing Symposium, IPPS 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages8
ISBN (Electronic)0818691670, 9780818691676
Publication statusPublished - 1991 Jan 1
Event5th International Parallel Processing Symposium, IPPS 1991 - Anaheim, United States
Duration: 1991 Apr 301991 May 2

Publication series

NameProceedings - 5th International Parallel Processing Symposium, IPPS 1991


Conference5th International Parallel Processing Symposium, IPPS 1991
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Computational Mathematics
  • Hardware and Architecture
  • Artificial Intelligence
  • Computer Networks and Communications
  • Computer Science Applications


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