@inproceedings{88cd3b9115c34a57ab7495b380588eaa,
title = "Proteus system architecture and organization",
abstract = "The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs hierarchical reconfigurable interconnection network with the highest level being a circuit switched Enhanced Hypercube serial interconnection network for internal data transfers. The system is designed to use 256 to 1,024 RISC processors. The processors use 1 M byte external Read/Write Allocating Caches for reduced multiprocessor contention. The system detects, locates and replaces faulty subsystems using redundant hardware to facilitate fault tolerance. The parallelism is directly controllable through an advanced software system for partitioning, scheduling and development.",
author = "Somani, \{Aran K.\} and Craig Wittenbrink and Haralick, \{Robert M.\} and Shapiro, \{Linda G.\} and Hwang, \{Jenq Neng\} and Chen, \{Chung Ho\} and Robert Johnson and Kenneth Cooper",
year = "1991",
month = jan,
day = "1",
doi = "10.1109/IPPS.1991.153793",
language = "English",
series = "Proceedings - 5th International Parallel Processing Symposium, IPPS 1991",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "287--294",
booktitle = "Proceedings - 5th International Parallel Processing Symposium, IPPS 1991",
address = "United States",
note = "5th International Parallel Processing Symposium, IPPS 1991 ; Conference date: 30-04-1991 Through 02-05-1991",
}