Abstract
A high-performance partitionable parallel/pipeline architecture (P3A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P3A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining.
Original language | English |
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Pages (from-to) | 529-531 |
Number of pages | 3 |
Journal | Proceedings - International Conference on Pattern Recognition |
Volume | 2 |
Publication status | Published - 1990 |
Event | Proceedings of the 10th International Conference on Pattern Recognition - Atlantic City, NJ, USA Duration: 1990 Jun 16 → 1990 Jun 21 |
All Science Journal Classification (ASJC) codes
- Computer Vision and Pattern Recognition