P3A: A partitionable parallel/pipeline architecture for real-time image processing

C. Thomas Gray, Wentai Liu, Thomas Hughes, Ralph Cavin, Sh shing Chen

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

A high-performance partitionable parallel/pipeline architecture (P3A) that is capable of real-time image processing is discussed. The architecture consists of P disjoint pipes of L processors each, connected together through a novel wraparound memory. Many different problem classes, including shuffle-exchange, butterfly, and tree algorithms, can be easily mapped into P3A. The power of the architecture lies in its ability to exploit both the spatial and temporal aspects of concurrency balancing parallelism and pipelining.

Original languageEnglish
Pages (from-to)529-531
Number of pages3
JournalProceedings - International Conference on Pattern Recognition
Volume2
Publication statusPublished - 1990
EventProceedings of the 10th International Conference on Pattern Recognition - Atlantic City, NJ, USA
Duration: 1990 Jun 161990 Jun 21

All Science Journal Classification (ASJC) codes

  • Computer Vision and Pattern Recognition

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