PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

B. Maiti, P. J. Tobin, C. Hobbs, R. I. Hegde, F. Huang, D. L. O'Meara, D. Jovanovic, M. Mendicino, J. Chen, D. Connelly, O. Adetutu, J. Mogab, J. Candelaria, L. B. La

Research output: Contribution to journalConference articlepeer-review

35 Citations (Scopus)

Abstract

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with TiN gate. Issues associated with Leff and reliability are also discussed.

Original languageEnglish
Pages (from-to)781-784
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1998 Dec 1
EventProceedings of the 1998 IEEE International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1998 Dec 61998 Dec 9

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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