TY - JOUR
T1 - Quantified temperature effect in a CMOS image sensor
AU - Lin, Dong Long
AU - Wang, Ching Chun
AU - Wei, Chia Ling
N1 - Funding Information:
Manuscript received August 7, 2009; revised October 26, 2009. Current version published January 22, 2010. This work was supported in part by the National Science Council, Taiwan, under Grant NSC-98-2220-E-006-012. The review of this paper was arranged by Editor J. Tower. D.-L. Lin and C.-L. Wei are with the Department of Electrical Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: [email protected]; [email protected]). C.-C. Wang is with the R&D Department, Taiwan Semiconductor Manufacturing Company, Hsinchu 300, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2037389
PY - 2010/2
Y1 - 2010/2
N2 - In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local high-leakage nonuniformities induced by on-chip temperature variations were controlled by both a Peltier junction device and on-chip resistors. Two test chips were fabricated using TSMC 0.13-μm CIS processes and TSMC 1-poly 6-metal 0.18-μm process technology, respectively. As expected, fixed-pattern noise increased with temperature. To quantify the influence of temperature, the maximum depth of an affected region was defined as DAR. The experimental results revealed that the DAR index increased with either an increase in power consumption or a space reduction between the resistor and the pixel array. The DAR index not only characterized affected regions in the experiment but also provided a valuable reference regarding temperature protection for future imager designs.
AB - In recent years, CMOS image sensors (CISs) have increasingly become major players in the solid-state imaging market, a market in which charge-coupled device image sensors were once the dominant product. Exceptional circuit integration capability makes CMOS imagers suitable for implementation in a single-chip imaging system while inducing the temperature variation of an image sensor. In this paper, global and local high-leakage nonuniformities induced by on-chip temperature variations were controlled by both a Peltier junction device and on-chip resistors. Two test chips were fabricated using TSMC 0.13-μm CIS processes and TSMC 1-poly 6-metal 0.18-μm process technology, respectively. As expected, fixed-pattern noise increased with temperature. To quantify the influence of temperature, the maximum depth of an affected region was defined as DAR. The experimental results revealed that the DAR index increased with either an increase in power consumption or a space reduction between the resistor and the pixel array. The DAR index not only characterized affected regions in the experiment but also provided a valuable reference regarding temperature protection for future imager designs.
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U2 - 10.1109/TED.2009.2037389
DO - 10.1109/TED.2009.2037389
M3 - Article
AN - SCOPUS:76349115799
SN - 0018-9383
VL - 57
SP - 422
EP - 428
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 2
M1 - 5373944
ER -