RAMSES: A fast memory fault simulator

Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu

Research output: Contribution to journalConference articlepeer-review

19 Citations (Scopus)


In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terms of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.

Original languageEnglish
Pages (from-to)165-173
Number of pages9
JournalIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Publication statusPublished - 1999 Dec 1
EventProceedings of the 1999 IEEE International Symposium on Defect and Faulttolerance in VLSI Systems (DFT'99) - Albueqeurque, NM, USA
Duration: 1999 Nov 11999 Nov 3

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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