RAMSES: A fast memory fault simulator

Chi Feng Wu; Chih Tsun Huang; Cheng Wen Wu

doi:10.1109/DFTVS.1999.802882

RAMSES: A fast memory fault simulator

Chi Feng Wu, Chih Tsun Huang, Cheng Wen Wu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N³) to O(N²), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.

Original language	English
Title of host publication	Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	165-173
Number of pages	9
ISBN (Electronic)	076950325X, 9780769503257
DOIs	https://doi.org/10.1109/DFTVS.1999.802882
Publication status	Published - 1999 Jan 1
Event	1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 - Albuquerque, United States Duration: 1999 Nov 1 → 1999 Nov 3

Publication series

Name	Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999

Conference

Conference	1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999
Country	United States
City	Albuquerque
Period	99-11-01 → 99-11-03

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/DFTVS.1999.802882

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Wu, C. F., Huang, C. T., & Wu, C. W. (1999). RAMSES: A fast memory fault simulator. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 (pp. 165-173). [802882] (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DFTVS.1999.802882

Wu, Chi Feng ; Huang, Chih Tsun ; Wu, Cheng Wen. / RAMSES : A fast memory fault simulator. Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 165-173 (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999).

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abstract = "In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from O(N3) to O(N2), where N is the memory capacity in terns of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.",

author = "Wu, {Chi Feng} and Huang, {Chih Tsun} and Wu, {Cheng Wen}",

year = "1999",

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booktitle = "Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999",

address = "United States",

note = "1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999 ; Conference date: 01-11-1999 Through 03-11-1999",

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Wu, CF, Huang, CT & Wu, CW 1999, RAMSES: A fast memory fault simulator. in Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999., 802882, Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, Institute of Electrical and Electronics Engineers Inc., pp. 165-173, 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999, Albuquerque, United States, 99-11-01. https://doi.org/10.1109/DFTVS.1999.802882

RAMSES : A fast memory fault simulator. / Wu, Chi Feng; Huang, Chih Tsun; Wu, Cheng Wen.

Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 165-173 802882 (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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Wu CF, Huang CT, Wu CW. RAMSES: A fast memory fault simulator. In Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 165-173. 802882. (Proceedings - 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 1999). https://doi.org/10.1109/DFTVS.1999.802882