RAMSES-FT: A fault simulator for flash memory testing and diagnostics

Kuo Liang Cheng, Jen Chieh Yeh, Chih Wea Wang, Chih Tsun Huang, Cheng Wen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

34 Citations (Scopus)


In this paper we present a fault simulator for flash memory testing and diagnostics, called RAMSES-FT. The fault simulator is designed for easy inclusion of new fault models by adding their fault descriptors without modifying the simulation engine. The flash memory fault models are discussed, based on the failures defined in the IEEE 1005 Standard. Both the NOR-type and NAND-type flash memory architectures are covered. Our flash memory fault simulator uses a parallel simulation strategy to reduce the simulation time complexity from O(N3) to O(N2), where N is the number of cells. With the proposed scaling method for March tests, the simulation time complexity is further reduced to O(W2), where W is the word width of the memory. The fault simulator supports March algorithms as well as single memory operations, covering most of the flash memory tests. With RAMSES-FT we have developed a diagnostic algorithm that can distinguish the target flash memory faults.

Original languageEnglish
Title of host publicationProceedings - 20th IEEE VLSI Test Symposium, VTS 2002
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)0769515703
Publication statusPublished - 2002 Jan 1
Event20th IEEE VLSI Test Symposium, VTS 2002 - Monterey, United States
Duration: 2002 Apr 282002 May 2

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference20th IEEE VLSI Test Symposium, VTS 2002
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering


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