Abstract
This paper first presents a theory for rasterizing the class of two-dimensional problems which include signal/image processing, computer vision, and linear algebra. The rasterization theory is steered by an isomorphism relationship between the two-dimensional shuffle exchange network (2DSE) and the two-dimensional butterfly network (2DBN). Since in real-time applications, data are often acquired in a raster scan format, it is important to develop architectures to support the raster data structure. Algorithms are developed first by using 2DSE network, then transformed into 2DBN format. Rasterization architectures can be derived for the algorithms described by 2DBN format. In the PEACE project, we have been able to show that a single, fixed communication topology, namely 2DSE, provides solution times on a 2DSE parallel computing system that for many problems approach known theoretical lower bounds. Secondly, this paper presents the generic architectures and VLSI implementation examples for the rasterization structures.
| Original language | English |
|---|---|
| Pages (from-to) | 179-199 |
| Number of pages | 21 |
| Journal | Integration, the VLSI Journal |
| Volume | 6 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 1988 Jul |
All Science Journal Classification (ASJC) codes
- Software
- Hardware and Architecture
- Electrical and Electronic Engineering