TY - GEN
T1 - Re-visit blocking texture cache design for modern GPU
AU - Liou, Jhe Yu
AU - Chen, Chung Ho
PY - 2015/4/16
Y1 - 2015/4/16
N2 - Texture cache plays a significant position in GPU design especially in a limited memory bandwidth environment such as mobile SoC system. In this paper, we evaluate the 6D blocking texture cache design through a sophisticated GPU simulator using DRAM memory model. Our experiment reveals that using a larger block can take advantage of the spatial locality of texel accesses, however, fetching a larger block which requires several burst runs in DRAM access, results in poor memory access efficiency. As a result, the block size used has to match with the DRAM burst length for the best memory access efficiency.
AB - Texture cache plays a significant position in GPU design especially in a limited memory bandwidth environment such as mobile SoC system. In this paper, we evaluate the 6D blocking texture cache design through a sophisticated GPU simulator using DRAM memory model. Our experiment reveals that using a larger block can take advantage of the spatial locality of texel accesses, however, fetching a larger block which requires several burst runs in DRAM access, results in poor memory access efficiency. As a result, the block size used has to match with the DRAM burst length for the best memory access efficiency.
UR - http://www.scopus.com/inward/record.url?scp=84929358971&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84929358971&partnerID=8YFLogxK
U2 - 10.1109/ISOCC.2014.7087652
DO - 10.1109/ISOCC.2014.7087652
M3 - Conference contribution
T3 - ISOCC 2014 - International SoC Design Conference
SP - 288
EP - 289
BT - ISOCC 2014 - International SoC Design Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 11th International SoC Design Conference, ISOCC 2014
Y2 - 3 November 2014 through 6 November 2014
ER -