Re-visit blocking texture cache design for modern GPU

Jhe Yu Liou, Chung Ho Chen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Texture cache plays a significant position in GPU design especially in a limited memory bandwidth environment such as mobile SoC system. In this paper, we evaluate the 6D blocking texture cache design through a sophisticated GPU simulator using DRAM memory model. Our experiment reveals that using a larger block can take advantage of the spatial locality of texel accesses, however, fetching a larger block which requires several burst runs in DRAM access, results in poor memory access efficiency. As a result, the block size used has to match with the DRAM burst length for the best memory access efficiency.

Original languageEnglish
Title of host publicationISOCC 2014 - International SoC Design Conference
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages288-289
Number of pages2
ISBN (Electronic)9781479951260
DOIs
Publication statusPublished - 2015 Apr 16
Event11th International SoC Design Conference, ISOCC 2014 - Jeju, Korea, Republic of
Duration: 2014 Nov 32014 Nov 6

Publication series

NameISOCC 2014 - International SoC Design Conference

Other

Other11th International SoC Design Conference, ISOCC 2014
Country/TerritoryKorea, Republic of
CityJeju
Period14-11-0314-11-06

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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