Abstract
This paper describes the design of Fast Fourier Transform (FFT) processors for the Eureka-147 DAB system. We investigate several possible FFT implementations based on single-butterfly architecture and apply in-place memory structure to minimize the hardware requirement. We also present two simple but efficient approaches in partitioning the whole memory into several banks so as to increase the equivalent memory bandwidth between the memory unit and the butterfly unit, which can be implemented in either radix-2 or high-radix arithmetic. The first technique P-CG is a unified prototype that transforms the partitioning problem into the coloring solution on the corresponding conflict graph, while its variant, P-DF arrangement, is developed for reducing the relatively complicated coloring process required in the case of long FFTs. The resulting architecture has the following characteristics: (1) the whole memory can be systematically partitioned into several individual banks and (2) the implementation can be derived in a simple way with regular controlling circuitry. Implementation results demonstrate the applicability of our work to the targeted DAB channel demodulator and the advantages over previous solutions.
Original language | English |
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Pages (from-to) | 269-280 |
Number of pages | 12 |
Journal | Journal of the Chinese Institute of Electrical Engineering, Transactions of the Chinese Institute of Engineers, Series E/Chung KuoTien Chi Kung Chieng Hsueh K'an |
Volume | 10 |
Issue number | 3 |
Publication status | Published - 2003 Aug |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering