Reconfigurable architecture for deinterlacer based on algorithm/ architecture co-design

Gwo-Giun Lee, Ming Jiun Wang, Bo Han Chen, Jiunfu Chen, Ping Keng Jao, Ching Jui Hsiao, Ling Fei Wei

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.

Original languageEnglish
Pages (from-to)181-189
Number of pages9
JournalJournal of Signal Processing Systems
Volume63
Issue number2
DOIs
Publication statusPublished - 2011 May 1

Fingerprint

Reconfigurable architectures
Reconfigurable Architectures
Co-design
Reconfiguration
Data Flow
Design Methodology
Language Modeling
Adaptability
Computer hardware
Interpolation
Silicon
Interpolate
Hardware
Path
Resources
Motion
Architecture
Costs
Actors

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Theoretical Computer Science
  • Signal Processing
  • Information Systems
  • Modelling and Simulation
  • Hardware and Architecture

Cite this

Lee, Gwo-Giun ; Wang, Ming Jiun ; Chen, Bo Han ; Chen, Jiunfu ; Jao, Ping Keng ; Hsiao, Ching Jui ; Wei, Ling Fei. / Reconfigurable architecture for deinterlacer based on algorithm/ architecture co-design. In: Journal of Signal Processing Systems. 2011 ; Vol. 63, No. 2. pp. 181-189.
@article{4d8e9150fe1745abbcba8f9e7ffe6279,
title = "Reconfigurable architecture for deinterlacer based on algorithm/ architecture co-design",
abstract = "This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.",
author = "Gwo-Giun Lee and Wang, {Ming Jiun} and Chen, {Bo Han} and Jiunfu Chen and Jao, {Ping Keng} and Hsiao, {Ching Jui} and Wei, {Ling Fei}",
year = "2011",
month = "5",
day = "1",
doi = "10.1007/s11265-009-0388-6",
language = "English",
volume = "63",
pages = "181--189",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer New York",
number = "2",

}

Reconfigurable architecture for deinterlacer based on algorithm/ architecture co-design. / Lee, Gwo-Giun; Wang, Ming Jiun; Chen, Bo Han; Chen, Jiunfu; Jao, Ping Keng; Hsiao, Ching Jui; Wei, Ling Fei.

In: Journal of Signal Processing Systems, Vol. 63, No. 2, 01.05.2011, p. 181-189.

Research output: Contribution to journalArticle

TY - JOUR

T1 - Reconfigurable architecture for deinterlacer based on algorithm/ architecture co-design

AU - Lee, Gwo-Giun

AU - Wang, Ming Jiun

AU - Chen, Bo Han

AU - Chen, Jiunfu

AU - Jao, Ping Keng

AU - Hsiao, Ching Jui

AU - Wei, Ling Fei

PY - 2011/5/1

Y1 - 2011/5/1

N2 - This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.

AB - This paper presents the algorithm and reconfigurable architecture of motion-adaptive deinterlacer for high-definition video. The content-adaptability of algorithm and the reconfiguration of architecture are concurrently explored by algorithm/architecture co-design methodology and Caltrop actor language (CAL) modeling of the dataflow. In the design methodology we employed, the CAL dataflow model is also very helpful in the verification of our deinerlacer. The proposed algorithm and architecture design of deinterlacer is more cost-efficient than two recently proposed works in terms of algorithmic performance and silicon area of VLSI implementation. Moreover, data path reconfiguration efficiently enables various interpolation schemes using less computational resource of hardware than non-reconfigurable architecture.

UR - http://www.scopus.com/inward/record.url?scp=79954595087&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79954595087&partnerID=8YFLogxK

U2 - 10.1007/s11265-009-0388-6

DO - 10.1007/s11265-009-0388-6

M3 - Article

VL - 63

SP - 181

EP - 189

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 2

ER -