TY - JOUR
T1 - Reconfigurable architecture for entropy decoding and inverse transform in H.264
AU - Lo, Chia Cheng
AU - Tsai, Shang Ta
AU - Shieh, Ming Der
N1 - Funding Information:
This work was supported in part by the National Science Council of R.O.C. under grant NSC 98-2220-E-006-004. The authors are from the Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan. (e-mail: shiehm@mail.ncku.edu.tw). Contributed Paper Manuscript received 06/10/10 Current version published 09/23/10 Electronic version published 09/30/10. 0098 3063/10/$20.00 © 2010 IEEE
PY - 2010/8
Y1 - 2010/8
N2 - Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.
AB - Reconfigurable hardware is an effective design option for dealing with the increasing demands of flexibility and computation power in system design. This paper explores techniques to combine the two entropy decoding methods defined in the H.264 standard, context-based adaptive binary arithmetic coding (CABAC) and context-based adaptive variable length coding (CAVLC), using a coarse-grain reconfigurable architecture. An analyzing of the similarities and differences between these two decoding processes shows that CAVLC can be effectively merged into a CABAC decoder. Experimental results show that about 1.5K gates can be saved using the proposed reconfigurable cell (RC) architecture, which corresponds to a 25.4% area savings in the implementation of the CAVLC decoder. Using the idle time in RC arrays, the base cell can be extended to carry out the inverse transform with very limited overhead. The proposed entropy decoder design, which operates at 66 MHz, can decode video sequences at Baseline and Main profiles at Level 3.0 under the real-time constraint.
UR - http://www.scopus.com/inward/record.url?scp=78149237561&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=78149237561&partnerID=8YFLogxK
U2 - 10.1109/TCE.2010.5606311
DO - 10.1109/TCE.2010.5606311
M3 - Article
AN - SCOPUS:78149237561
SN - 0098-3063
VL - 56
SP - 1670
EP - 1676
JO - IEEE Transactions on Consumer Electronics
JF - IEEE Transactions on Consumer Electronics
IS - 3
M1 - 5606311
ER -