Reconfigurable Edge via Analytics Architecture

Shih Yu Chen, Gwo Giun Chris Lee, Tai Ping Wang, Chin Wei Huang, Jia Hong Chen, Chang Ling Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

As artificial intelligence (AI) algorithms requiring high accuracy become exceedingly more complex and Edge/IoT generated data becomes increasingly bigger, flexible reconfigurable processing is crucial in the design of efficient smart edge systems requiring low power and is introduced in this paper. In AI, analytics algorithms are typically used to analyze speech, audio, image video data, etc. In current cross-level system design methodology different algorithmic realizations are analyzed in the form of dataflow graphs (DFG) to further increase efficiency and flexibility in constituting 'analytics architecture'. Having information on both algorithmic behavior and architectural information including software and hardware, the DFG so introduced provides a mathematical representation which, as opposed to traditional linear difference equations, better models the underlying computational platform for systematic analysis thus providing flexible and efficient management of the computational and storage resources. In our analytics architecture work, parallel and reconfigurable computing are formulated via DFG which are analogous to the analysis and synthesis equations of the well-known Fourier transform pair. In parallel computing, a connected component is eigen-decomposed to unconnected components for concurrent processing. For computation resource saving, commonalities in DFGs are analyzed for reuse when synthesizing or reconfiguring the edge platform. In this paper, we specifically introduce lightweight edge upon which algorithmic convolution for Convolution Neural Network are eigen-transformed to matrix operations with higher symmetry which facilitates fewer operations, lower data transfer rate and storage anticipating lower power when synthesizing or reconfiguring the eigenvectors.

Original languageEnglish
Title of host publicationProceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages117-121
Number of pages5
ISBN (Electronic)9781538678848
DOIs
Publication statusPublished - 2019 Mar
Event1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 - Hsinchu, Taiwan
Duration: 2019 Mar 182019 Mar 20

Publication series

NameProceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019

Conference

Conference1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
CountryTaiwan
CityHsinchu
Period19-03-1819-03-20

All Science Journal Classification (ASJC) codes

  • Artificial Intelligence
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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